1. Field of the Invention
The present invention relates to the control of multiple disk drives within computer systems, and more particularly to a method for distributing data across a multiple disk array for personal computer systems
2. Description of the Related Art
Microprocessors and the personal computers which utilize them have become more power over the recent years. Currently available personal computers have capabilities easily exceeding the mainframe computers of 20 to 30 years ago and approach the capabilities of many computers currently manufactured. Microprocessors having word sizes of 32 bits wide are now widely available, whereas in the past 8 bits was conventional and 16 bits was common.
Personal computer systems have developed over the years and now uses are being discovered daily. The uses are varied and, as a result, have different requirements for various subsystems forming a complete computer system. Because of production volume requirements and the reduced costs as volumes increase, it is desirable that as many common features as possible are combined into high volume units. This has happened in the personal computer area by developing a basic system unit which generally contains a power supply, provisions for physically mounting the various mass storage devices and a system board, which in turn incorporates a microprocessor, microprocessor related circuitry, connectors for receiving circuit boards containing other subsystems, circuitry related to interfacing the circuit boards to the microprocessor, and memory. The use of connectors and interchangeable circuit boards allows subsystems of the desired capability for each computer system to be easily incorporated into the computer system. The use of interchangeable circuit boards necessitated the developement of an interface or bus standard so that the subsystems could be easily designed and problems would not result from incompatible decisions by the system unit designers and the interchangeable circuit board designers.
The use of interchangeable circuit boards and an interface standard, commonly called a bus specification because the various signals are provided to all the connectors over a bus, was incorporated into the original International Business Machines Corporations (IBM) personal computer, the IBM PC. The IBM PC utilized in Intel Corporation 8088 as the microprocessor. The 8088 has an 8 bit, or 1 byte, external data interface but operates on a 16 bit word internally. The 8088 has 20 address lines, which means that it can directly address a maximum of 1 Mbyte of memory. In addition, the memory components available for incorporation in the original IBM PC were relatively slow and expensive as compared to current components. The various subsystems such as video output units or mass storage units, were not complex and also had relatively low performance levels because of the relative simplicity of the devices available at a reasonable costs at that time.
With these various factors and the component choices made in mind, an interface standard was developed and used in the IBM PC. The standard utilized 20 address lines and 8 data lines, had individual lines to indicate input or output (I/O) space or memory space read/write operations, and had limited availability of interrupts and direct memory access (DMA) channels. The complexity of the available components did not require greater flexibility or capabilities of the interface standard to allow the necessary operations to occur. This interface standard was satisfactory for a number of years.
As is inevitable in the computer and electronics industry, capabilities of the various components available increased dramatically. Memory component prices dropped and capacities and speeds increased. Performance rate and capacities of the mass storage subsystems increased, generally by the incorporation of hard disk units for previous floppy disk units. The video processor technology improved so that high resolution color systems were reasonably affordable. These developments all pushed the capabilities of the existing IBM PC interface standard so that the numerous limitations in the interface standard became a problem. With the introduction by Intel Corporation of the 80286, IBM developed a new, more powerful personal computer called the AT. The 80286 has a 16 bit data path and 24 address lines so that it can directly address 16 Mbytes of memory. In addition, the 80286 has an increased speed of operation and can easily perform many operations which taxed 8088 performance limits.
It was desired that the existing subsystem circuit boards be capable of being used in the new AT, so the interface standard used in the PC was utilized and extended. A new interface standard was developed, which has become known as the industry standard architecture (ISA). A second connector for each location was added to contain additional lines for the signals used in the extension. These lines included additional address and data lines to allow the use of the 24 bit addressing capability and 16 bit data transfers, additional interrupt and direct memory access lines and lines to indicate whether the subsystem circuit board was capable of using the extended features. While the address values are presented by the 80286 microprocessor relatively early in the operation cycle, the PC interface standard could not utilize the initial portions of the address availability because of different timing standards for the 8088 around which the original PC interface was designed. This limited the speed at which operations could occur because they were now limited to the interface standard memory timing specifications and could not operate at the rates available with the 80286. The newly added address lines included address signals previous available, but the newly added signals were available at an early time in the cycle. This change in the address signal timing allowed operations which utilized the extended portions of the architecture to operate faster.
With a higher performance components available, it became possible to have a master unit other than the system microprocessor or direct memory access controller operating the bus. However, because of the need to cooperate with circuit boards which operated under the new 16 bit standard or the old 8 bit standard, each master unit was required to understand and operate with all the possible combinations of circuit boards. This increased the complexity of the master unit and resulted in a duplication of components, because the master unit had to incorporate many of the functions and features already performed by the logic and circuitry on the system board and other master units. Additionally, the master unit was required to utilize the direct memory access controller to gain control of the bus, limiting prioritizing and the number of master units possible in a given computer system.
The capability of components continued to increase. Memory speeds and sizes increased, mass storage units and size increased, video unit resolutions increased and Intel Corporation introduced the 80386. The increased capabilities of the components created a desire for the use of master units, but the performance of a master unit was limited by the ISA specification and capabilities. The 80386 could not be fully utilized because it offered the capability to directly address 4 Gbytes of memory using 32 bits of address and could perform 32 bit wide data transfers, while the ISA standard allowed only 16 bits of data and 24 bits of address. The local area network (LAN) concept, where information and file stored on one computer called server and distributed to local work stations having limited or no mass storage capabilities, started becoming practical with the relatively low cost of high capability components needed for adequate servers and the low cost of the components for work stations. An extension similar to that performed in developing the ISA could be implemented to utilize the 80386""s capabilities. However, this type of extension would have certain disadvantages. With the advent of the LAN concept and the high performance requirements of the server and of video graphics work stations used in computer-added design and animation work, the need for a very high data transfer rates became critical. An extension similar to that performed in developing the ISA would not provide this capability, even if slightly shorter standards cycle was provided, because this would still leave the performance below desired levels.
With the increased performance of computer systems, it became apparent that mass storage subsystems, such as fixed disk drives, played an increasingly important role in the transfer data to and from the computer system. In the past few years, a new trend in mass storage subsystems has emerged for improving data transfer performance, capacity and reliability. This is generally known as a disk array subsystem. One key reason for wanting to build a disk array subsystem is to create a single logical device that has very high data transfer rate. This may be accomplished by xe2x80x9cgangingxe2x80x9d multiple standard disk drives together and transferring data to or from these drives to the system memory. If n drives are ganged together, then the effective data transferred rate is increased n times. This technique, called xe2x80x9cstripingxe2x80x9d originated in the super computing environment where the transfer of large amounts of data to and from secondary storage is a frequent requirement. With this approach, the end physical drives would become a single logical device and may be implemented either through software or hardware.
A number of reference articles on the design of disk arrays have been published in recent years. These include xe2x80x9cSome Design Issues of Disk Arraysxe2x80x9d by Spencer Ng, April 1989 IEEE; xe2x80x9cDisk Array Systemsxe2x80x9d by Wes E. Meador, April 1989 IEEE; and xe2x80x9cA Case for Redundant Arrays of Inexpensive Disks (RAID)xe2x80x9d by D. Patterson, G. Gibson and R. Catts report No. UCB/CSD 87/391, December 1987, Computer Science Division, University of California, Berkley, Calif.
The present invention is directed towards a method and apparatus for an intelligent disk array controller, permitting the controller to manage the operation of an array of up to eight(8) standard integrated disk drives connected in drive pairs without significant supervision by the computer system host. Specifically, the present invention is directed toward the translation of logical I/O request from the computer system host or other device driver to specific physical drive commands used to distribute the data among the drives in the disk array. Further, the present invention is directed to a technique which will maximize performance based upon the operating environment of the host computer system. The improved performance results from improved subsystem performance due to the use of a highly specialized subsystem controller. Further, improved system performance is attained by minimizing the level of host processing. The disk array controller of the present invention permits the host processor or device driver to be independent of the physical configuration of the array and drives which make up the disk array; the data distribution technique; drive parity operations, and most error recover and fault tolerance activities.
The communication mechanism between the disk array controller and device driver software is through a bus master interface controller or a compatibility port interface controller. The bus master controller is capable of data transfer rates across the EISA bus at a rate of 32 Mbytes per seconds using 32 bit bus master burst DMA (type C) cycles as defined in the EISA specification through bus master interface controller. The data transfer rate from a single drive in the array is approximately 2 Mbytes per second, which, when implemented over four disk drives, allows burst data rate of 8 Mbytes per second, a major improvement over existing transfer rates for a single EISA integrated disk drive.
In the present invention a local processor within the disk array controller receives information packets or xe2x80x9clogical requestsxe2x80x9d from the host processor specifying a disk I/O command. The information packet includes information relating to the specific command, the priority of the command, and addresses within system memory for the sources or targets for the data transfer to or from the disk array. This information is, by itself, insufficient to carry out disk level operations. The local processor breaks these logical requests into a series of xe2x80x9cdrive requestsxe2x80x9d which include drive specific information including disk drive number, head, cylinder and sector information based upon the type of disks within the array, the particular controller, and type of operating system being run on the host computer. Each of the drive requests maintains a relationship with the parent logical request, such that the drive request also contains information relating to the source or target address in system memory for the transfer. The drive requests are then scheduled for execution by the disk array controller. The actual transfer of data between the disk array and system memory is managed by a bus master or compatibility port controller within the disk array controller. Thus, the present invention permits the system host processor to issue logical commands as opposed to the creation of drive requests to be carried out by the disk array controller, thereby significantly reducing system processor overhead and increasing system efficiency.
The present invention is also capable of initializing a logical unit configuration based upon information which exists within the reserved sectors on disk within the disk array. In configuring the logical unit, the present invention reads the reserved sectors for all of the disks within the array and determines which, if any, of the disks have a valid but inconsistent configuration image. If there exist more than one valid configuration image among the disks within the logical unit, the present invention will xe2x80x9cvotexe2x80x9d as to which of the valid configurations is to be used as a xe2x80x9ctemplatexe2x80x9d for the remaining disks within the array. Further, if none of the disks have a valid configuration, the computer system including the present invention will initiate the operation of a utility designed to create a valid configuration.